Memory devices are used to store data in digital electronic devices such as computers. The demand for large memory systems with high bandwidth and low power consumption has increased during recent years. Early multi die memory devices in digital electronics included a plurality of dies connected in parallel to a common bus such a system is said to be connected by a multi-drop bus. Multi-drop connection with several memory device dies connected to a common bus in parallel is commonly used for a large memory system.
FIG. 1 shows a prior art embodiment of multi-drop connection with double sided memory device mounding. The memory device dies 1 and 2 are mounted to the first side 7 of a substrate 6. Dies 3 and 4 are mounted on the opposite side of substrate 6 directly opposed to dies 1 and 2 respectively. Substrate 6 may be a multi-layered PCB, or other similar substrate such as a ceramic wafer. Substrate 6 often includes internally routed signal traces 9 and 10 between memory device dies 1-4. Stub through vias 11-18 allow signal traces 9 and 10 to connect to the opposite surfaces 7 and 8 of substrate 6. Stub through vias 11-18 commonly terminate in pads 21-28 on surfaces 7 and 8. Pads 21-28 are configured to connect to solder balls 29 or other connections from memory device dies 1-4 to signal traces. Stub through via allows the solder ball 29 or other connection from memory device dies to the signal traces 9 and 10. Vias 11-18 are manufactured on a larger pitch than signal traces 9 and 10 to afford extra width, and the use of several such vias can limit the number of traces that can be routed through a single layer of the substrate. This may force additional layers and extra costs. The number of memory device dies connected to a bus is large. Capacitive loading of each memory device die and long trace cause large capacitive loading on the bus so that it is hard to get high bandwidth. And large capacitive loading means large power consumption.
More recent designs use interconnection of a plurality of memory device dies are connected in serial. The reason for doing so is to reduce capacitive loading on the bus by limiting the number of memory device dies. Such an array of memory dies is commonly referred to as a Daisy Chain. A variation connects the last die in the Daisy Chain to the first die to form a loop, such a device is referred to as being loop chained. FIG. 2 shows a prior art embodiment of a daisy chained interconnection or a loop chained interconnection with double sided memory device mounting. The memory device dies 31 and 32 are mounted to the first side 37 of a substrate 36. Dies 33 and 34 are mounted on the opposite side 38 of substrate 36 substantially opposite dies 31 and 32. Substrate 36 may be a multi-layered PCB, or other similar substrate such as a ceramic wafer. Substrate 36 includes internally routed signal traces 39 between die 31 and the outside and 40 between memory device dies 31 and 32, 41 between 32 and 34, 42 between 34 and 33 and 43 between 33 and the outside. Stub through vias 46-54 allow connections to the solder balls 56 or other connection from memory device dies 31-34 to signal traces 39-43. Because memory device dies 31-34 are connected each other point to point, capacitive loading of memory device dies 31-34 on the bus are smaller and the lengths of traces 36-43 are shorter than that of multi-drop connection of FIG. 1 so that the total capacitive loading on the bus are reduced. However there are still traces 36-54 between memory device dies and so that it is hard to get high bandwidth and low power consumption.